Currently, a large number of functional blocks in an embedded system are realized as software for flexibility. However, together with the software, fixed hardware Intellectual properties (IPs) or application-specific integrated circuits (ASICs) reduce flexibility of a whole system but are still used to improve performance.
Coarse-grained reconfigurable arrays (CGRAs) are suggested to improve both flexibility and performance. Typical CGRAs include a reconfigurable array of processing elements (PEs) in order to increase performance due to parallel execution. Each PE is a small-sized execution unit that can be dynamically configured to execute simple operations such as arithmetic or logical operations. Also, interconnection between the PEs may also be dynamically configured for efficient communications. Such dynamic configuration provides flexibility to CGRAs.